Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

46.3. Video Streaming FIFO IP Interfaces

Table 859.  Video Streaming FIFO IP Interfaces
Name Direction Width Description
Clocks and resets
main_clock_clk In 1 AXI4-S processing clock. Only when you turn off Dual clock.
main_reset_rst In 1 AXI4-S processing reset. Only when you turn off Dual clock
in_clock_clk In 1 AXI4-S processing clock for the input interface domain. Only when you turn on Dual clock.
in_reset_rst In 1 AXI4-S processing reset for the input interface domain. Only when you turn on Dual clock.
out_clock_clk In 1 AXI4-S processing clock for the output interface domain. Only when you turn on Dual clock.
out_reset_rst In 1 AXI4-S processing reset for the output interface domain. Only when you turn on Dual clock.

Intel FPGA streaming video interfaces

Port name Direction Width Description
axi4s_vid_in_tdata In AXI4S data in.
axi4s_vid_in_tvalid In 1 AXI4-S data valid.
axi4s_vid_in_tuser In

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted.

axi4s_vid_in_tlast In 1 AXI4-S end of packet.
axi4s_vid_in_tready Out 1 AXI4-S data ready.
axi4s_vid_out_tdata Out 122 AXI4-S data in.
axi4s_vid_out_tvalid Out 1 AXI4-S data valid.
axi4s_vid_in_tuser Out 123

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted.

axi4s_vid_out_tlast Out 1 AXI4-S end of packet.
axi4s_vid_out_tready In 1 AXI4-S data ready.

122

The equation gives all tdata widths in these interfaces:

max (ceil((bits per color sample x number of color planes x pixels in parallel) / 8) x 8, 16)

123

The equation gives all tuser widths in these interfaces:

N = ceil (tdata width / 8)