Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

41.4. Unsharp Mask IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 716.   Unsharp Mask IP Registers

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_UNSHARP MASK as appropriate and with an optional REG suffix

Address Register Access Description
Parameterization registers
0x0000 VID_PID RO Read this register for the unsharp mask product ID. This register always returns 0x027C.
0x0004 VERSION RO Read this register for the version information for the Intel Quartus release that Intel uses to build the unsharp mask.
0x0008 LITE_MODE RO This register returns 1 because the IP operates in lite mode.
0x000C DEBUG_ENABLED RO Read this register to determine if Debug features are on.
0x0010 BITS_PER_SYMBOL RO Read this register to determine the bits per symbol.
0x0014 PIXELS_IN_PARALLEL RO Read this register to determine the pixels in parallel.
0x0018 MAX_WIDTH RO Read this register to determine the maximum frame width.
0x001C MAX_HEIGHT RO Read this register to determine the maximum frame height.
0x001F

to

0x013F
Reserved - Reserved
Control and debugging registers
0x0120 IMG_INFO_WIDTH RW

Write the expected width of incoming video fields. Changes to this register take effect at the next start of line.

The IP removes the extra pixels from fields wider than this setting. Narrower fields can result in the IP producing pixels from previous lines.

0x0124 IMG_INFO_HEIGHT RW

Write the expected height of incoming video fields. Changes to this register take effect at the next start of field.

The IP removes the extra lines from fields taller than this setting. Shorter fields can result in corrupted output pixels.

0x0128

to

0x013F
Reserved - Reserved.
0x0140 STATUS RO

Bit 0: status bit, which goes high when the IP starts producing the first frame. It goes low after the IP finishes producing the last line of the frame. It returns high when the IP starts producing the next frame.

Applications that need to know when the IP produces frames can poll this status register.

1 = Unsharp mask is producing a video field, 0 otherwise.

0x01443 Reserved - Reserved
0x0148 STRENGTH RW

14 bits.

2 integer bits and 12 fractional bits

Set STRENGTH to 0 for bypass mode.

Positive strengths sharpen the edges.

Negative strengths blur the edges.

Increase the magnitude of STRENGTH to increase the unsharp mask effect.