Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

30.2. Genlock Signal Router IP Parameters

The IP offers compile-time parameters.
Table 474.  Genlock Signal Router IP Parameters
Parameter Values Description
Build configuration
Length of clock pulse 1 to 32 The number of clocks for the output genlock pulse
Number of genlock inputs 1 to 32 The number of input ports
Number of genlock outputs 1 to 32 The number of output ports
General-purpose input conduit True or false Turn on a general-purpose input port for this IP
Number of bits of GPI 1 to 32 The number of bits for the general-purpose input interface
General-purpose output conduit True or false Turn on a general-purpose output port for this IP
Number of bits of GPO 1 to 32 The number of bits for the general-purpose output interface
Genlock output type Discrete timing signals, Clocks only Select the type for all available outputs
Genlock Input Type: AXI-S FR (Per Input Interface)
Number of bits per color plane 8 to 16 The number of bits per color sample at the input
Number of pixels in parallel 1 to 8 The number of pixels transmitted every clock cycle.
Number of color planes 1 to 4 The number of color planes per pixel
AXI4-S FR interface TREADY True or false Enable the TREADY signal as part of the full-raster interface
Genlock Input Type: Discrete timing Clocked Video signals (Per Input Interface)
Clock 0 to 1 Discrete input interface has Input clock signal
F 0 to 1 Discrete input interface has Input field signal
V 0 to 1 Discrete input interface has Input vertical blanking signal
H 0 to 1 Discrete input interface has Input horizontal blanking signal
V sync 0 to 1 Discrete input interface has Input vertical sync signal
H sync 0 to 1 Discrete input interface has Input horizontal sync signal
Toggle 0 to 1 Discrete input interface has Input field pulse signal
Pulse 0 to 1 Discrete input interface has Input field toggle signal
Figure 75. Genlock Signal Router IP GUI