Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

45.4. Video Frame Writer IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 820.   Video Frame Writer IP Registers

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_VIDEO FRAME WRITER as appropriate and with an optional REG suffix.

Address Register Access Description
Parameterization registers
0x0000 VID_PID RO Read this register for the Video Frame Writer product ID. This register always returns 0x6AF7_0249.
0x0004 VERSION RO Read this register for the version information for the Video Frame Writer.
0x0008 LITE_MODE RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO Read this register to determine if Debug features is on.
0x0010 MAX_HEIGHT RO Read this register to determine the maximum supported frame height.
0x0014 MAX_WIDTH RO Read this register to determine the maximum supported frame width.
0x0018 BITS_PER_SYMBOL RO Read this register for the number of bits per symbol configured.
0x001C NUMBER_OF_COLOR_PLANES RO Read this register for the number of color planes.
0x0020 PIXELS_IN_PARALLEL RO Read this register for the number of pixels in parallel.
0x0024 PACKING RO Read this register for the pixel packing scheme.
0x0028 to 0x00FF RESERVED
Interrupt registers
0x0100 IRQ_CONTROL RW IRQ control. Set this register to configure interrupts
0x0104 IRQ_STATUS RW

Read this status register to see if an interrupt fired.

0x0108 to

0x011F

RESERVED

Control and Debug registers

0x0120 IMG_INFO_WIDTH RW / RO Image information width.
0x0124 IMG_INFO_HEIGHT RW / RO Image information height.
0x0128 IMG_INFO_INTERLACE RO

Image information interlace.

0x012C RESERVED RW / RO Reserved.
0x0130 IMG_INFO_COLORSPACE RW / RO Image information color space
0x0134 IMG_INFO_SUBSAMPLING RW / RO Image information subsampling.
0x0138 IMG_INFO_COSITING RW / RO Image information cositing.
0x013C IMG_INFO_FIELD_COUNT RW / RO Field count image information.
0x0140 STATUS RO Status register
0x0144 BUFFER_AVAILABLE RO Buffer available.
0x0148 BUFFER_WRITE_COUNT RO Buffer write count

This register is reset after a write to the COMMIT register.

0x014C BUFFER_START_ADDRESS RO

The start address of the buffer the IP most recently writes.

0x0150 BUFFER_F1_FLAG RO

Buffer F1 flag.

0x0154 BUFFER_FIELD_WIDTH RO Buffer field width,
0x0158 BUFFER_FIELD_HEIGHT RO Buffer field height.
0x015C RESERVED
0x0160 FIELD_COUNT RO The value from the end-of-field packet of the most recently written buffer.
0x0164 COMMIT RW

Write any value to the COMMIT register to commit new RW register values and request an update to the new settings.

0x0168 BUFFER_ACKNOWLEDGE RW

Write to the BUFFER_ACKNOWLEDGE register to reset the BUFFER_AVAILABLE register.

BUFFER_ACKNOWLEDGE is the one exception to the need to write to COMMIT after updating a RW register.

0x016C RUN RW

Set the required operating mode:

0 - Frame writer is not running (stopped)

1 - Frame writer is free-running

2 - Frame writer is not running (stopped)

3 - Frame writer is in single-shot mode.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field.

0x0170 NUM_BUFFERS RW

The number of buffers.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field.

0x0174 BUFFER_BASE RW

Buffer base address.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field

0x0178 INTER_BUFFER_OFFSET RW

Interbuffer address increment.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field

0x017C INTER_LINE_OFFSET RW

Interline address increment.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field

0x0180 to 0x0193 RESERVED
0x0194

IRQ_LINE_THRESHOLD

RW

IRQ line threshold.

0x0198 OVERWRITE_BROKEN RW Set to overwrite broken fields..

Register Bit Descriptions

Table 821.  VID_PID
Name Bits Description
Frame writer version ID and product ID 31:0

This register always returns 0x6AF7_0249

  • 15:0 is the product ID and always returns 0x0249
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 822.  VERSION
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
QPDS patch revision 15:8 Returns 0x00
QPDS update revision 23:16 Updated for each release. For 23.2, returns 0x02
QPDS major revision 31:24 Updated for each release. For 23.2, returns 0x17.
Table 823.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 824.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 825.  MAX_HEIGHT
Name Bits Description
Max height 31:0 Returns the maximum supported frame height.
Table 826.  MAX_WIDTH
Name Bits Description
Max width 31:0 Returns the maximum supported frame width.
Table 827.  BITS_PER_SYMBOL
Name Bits Description
Bits per symbol 31:0 Returns the number of bits per symbol that the Intel Streaming Video output is configured for.
Table 828.  NUMBER_OF_COLOR_PLANES
Name Bits Description
Number of color planes 31:0 Returns the number of color planes that the Intel Streaming Video output is configured for.
Table 829.  PIXELS_IN_PARALLEL
Name Bits Description
Number of pixels in parallel 31:0 This register returns the number of pixels in parallel that the Intel Streaming Video output is configured for.
Table 830.  PACKING
Name Bits Description
Packing 31:0

This register returns the packing scheme that the IP uses:

0 = Perfect packing

1 = Color packing

2 = Pixel packing

Table 831.  IRQ_CONTROL
Name Bit Description
Field_write_irq 0

Set the field_write_irq bit of the IRQ_CONTROL register to enable interrupts on completing field writes. Clear to disable interrupts on completing field writes.

Line_write_irq 1

Set the line_write_irq bit of the IRQ_CONTROL register to enable interrupts on completion of line writes. Clear the line_write_irq bit to disable interrupts on completion of line writes.

Select which line generates the interrupt by programing IRQ_LINE_THRESHOLD with the required line number. Line numbers start from 0.

Table 832.  IRQ_STATUS
Name Bit Description
Field_write_irq 0

The IP sets the field_write_irq bit of the IRQ_STATUS register if the interrupt fires.

Write to the field_write_irq bit of the IRQ_STATUS register to clear down the interrupt.

line_write_irq 1 The IP sets the line_write_irq bit of the IRQ_STATUS register if the interrupt fires. Write to the line_write_irq bit of the IRQ_STATUS register to clear down the interrupt
Table 833.  IMG_INFO_WIDTH
Name Bits Description
width 16:0

The field width that the writer IP uses when writing to memory.

If Lite mode is on, this register is RW. Write the expected width in pixels of incoming fields.

If Lite mode is off, if debug features are on, this register is RO and contains the field width received via the image information packet.

The IP removes extra pixels from received fields wider than IMG_INFO_WIDTH. The IP writes narrower fields leaving pixels from any previous fields in the buffer unmodified.

After any changes to this register write to the COMMIT register, which takes effect at the next start of field.

Table 834.  IMG_INFO_HEIGHT
Name Bits Description
height 16:0

The field height that the writer uses when writing to memory.

If Lite mode is on, this register is RW. Write the expected height in lines of incoming fields.

If Lite mode is off, if debug features are on, this register is RO and contains the field height received via the image information packet.

The IP removes extra lines from fields received that are taller than IMG_INFO_HEIGHT.

Shorter fields leave pixels from any previous fields in the buffer unmodified.

After any changes to this register write to the COMMIT register, which takes effect at the next start of field.

Table 835.   IMG_INFO_INTERLACE
Name Bits Description
interlace 3:0

If Lite mode is on, the IP stores interlaced fields in the same way as progressive frames by the frame writer, so you do not need to set this nibble.

If Lite mode is off, if debug features are on, this register is RO and contains the interlaced nibble received via the image information packet.

Table 836.   IMG_INFO_COLORSPACE
Name Bits Description
colspace 6:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the colorspace received via the image information packet.

Table 837.  IMG_INFO_SUBSAMPLING
Name Bits Description
subsampling 1:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the subsampling received via the image information packet.

Table 838.  IMG_INFO_COSITING
Name Bits Description
co-siting 1:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the cositing received via the image information packet.

Table 839.  IMG_INFO_FIELD_COUNT
Name Bits Description
field_count 5:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the field_count received via the image information packet.

Table 840.  STATUS
Name Bit Description
Status 0 Read this register to determine the status of the frame writer. The IP sets the status bit if the write is currently writing a frame, and returns to 0 in between frames.
Pending run-time control 1 Read this register to determine if the IP has any pending register writes to commit. This bit goes high when a write occurs to one of the control registers and returns low at the end of the current frame after a write to the COMMIT register. If the frame writer is idle, this bit goes low directly after a write to the COMMIT register.
Table 841.   BUFFER_AVAILABLE
Name Bit Description
Buffer available 0

After you write a field, the IP sets this bit and sets the BUFFER_START_ADDRESS, BUFFER_FIELD_WIDTH, BUFFER_FIELD_HEIGHT and BUFFER_F1_FLAG registers.

Clear the BUFFER_AVAILABLE bit by writing to the BUFFER_ACKNOWLEDGE register. The IP does not update BUFFER_START_ADDRESS, BUFFER_FIELD_WIDTH, BUFFER_FIELD_HEIGHT and BUFFER_F1_FLAG registers until you clear BUFFER_AVAILABLE.

For a steady video input, software has the duration of one field (typically around 5-20 ms) to read the buffers and clear BUFFER_AVAILABLE before you lose any buffer information.

Table 842.  BUFFER_WRITE_COUNT
Name Bits Description
Write count 31:0

Increments with each buffer the IP writes and resets with a write to the COMMIT register.

If you set the OVERWRITE_BROKEN register, this counter does not increment for fields that the IP writes but subsequently overwrites.

Table 843.  BUFFER_START_ADDRESS
Name Bit Description
Start address 31:0

Provides the start address of the most recently written buffer.

The IP writes the first buffer to the address you specify with BUFFER_BASE.

Table 844.  BUFFER_F1_FLAG
Name Bit Description
F1 flag 0

If Lite mode is on, this bit provides the state of TUSER[1] for the most recently written buffer. The IP set this bit when it writes to interlaced F1 fields.

If Lite mode is off, the IP sets this to the binary AND of IntlaceNibble bits 3 and 2 from the image information packet.

Table 845.  BUFFER_FIELD_WIDTH
Name Bit Description
Field width 31:0

If Lite mode is on, the IP returns the current value in IMG_INFO_WIDTH.

If Lite mode is off, the IP sets these bits to the width in the image information packet.

Table 846.  BUFFER_FIELD_HEIGHT
Name Bit Description
Field height 31:0

If Lite mode is on, the IP returns the current value in IMG_INFO_HEIGHT.

If Lite mode is off, the IP sets these bits to the height in the image information packet.

Table 847.  FIELD_COUNT
Name Bit Description
Field count 15:0

If Lite mode is on this returns 0.

If Lite mode is off, the IP takes the value from the end of field packet of the most recently written buffer.

Table 848.  COMMIT
Name Bit Description
Commit 0

Write any value to the COMMIT register to commit new RW register values and request an update to the new settings.

The frame buffer updates to the new RW register settings at the next start of field.

The IP starts operating according to the new settings when you write the current. The IP lowers the pending_rtc bit in the status register at this time.

The BUFFER_ACKNOWLEDGE register is the only register that does not need to be followed by a write to commit.

Table 849.  BUFFER_ACKNOWLEDGE
Name Bit Description
Acknowledge 0

Write to the acknowledge bit to reset the BUFFER_AVAILABLE register.

You don't need to follow a write to the BUFFER_ACKNOWLEDGE register with a write to the COMMIT register for it to take effect.

Table 850.  RUN
Name Bits Description
Run 0

Set the run bit to start the IP writing fields.

Clear the run bit to stop the IP writing at the end of the current field.

Single shot 1

Set the single shot bit to configure single shot mode. The frame writer writes buffers until it reaches NUM_BUFFERS buffers and then switches to consume mode. The IP sets BUFFER_AVAILABLE register after the first field write completes. To perform another single-shot write, clear BUFFER_AVAILABLE by writing to BUFFER_ACKNOWLEDGE. BUFFER_AVAILABLE.

If this bit is clear, the IP operates in continuous free-running mode and after it reaches NUM_BUFFERS buffers, writing continues, starting at BUFFER_BASE again.

Use this mode with NUM_BUFFERS set to 1, or a small value.

After any changes to this register write to the COMMIT register, which take effect at the next start of field

Table 851.  NUM_BUFFERS
Name Bits Description
Num_buffers 23:0

The number of buffers. When all buffers are full, the frame writer wraps around and begins writing to BUFFER_BASE again unless you set the single shot bit of the RUN register is set.

After any changes to this register write to the COMMIT register, which take effect at the next start of field

Table 852.  BUFFER_BASE
Name Bit Description
Buffer_base 31:0 Frame writing resets to the buffer_base address whenever you commit a write to the RUN register.

After any changes to this register write to the COMMIT register, which take effect at the next start of field

Table 853.  INTER_BUFFER_OFFSET
Name Bits Description
Inter-buffer offset 31:0

Interbuffer address increment. To prevent fields overwriting one another in memory, you must set this so that the spacing between buffers is greater than the size of individual fields in memory.

Interbuffer offset must be word aligned

After any changes to this register write to the COMMIT register, which take effect at the next start of field

Table 854.  INTER_LINE_OFFSET
Name Bits Description
Inter-line offset 31:0

Interline address increment.

Usually set to the low byte of the next word address above

bytes per pixel * IMAGE_WIDTH.

To prevent lines overwriting one another in memory you must set this bit so it is equal or greater than the line width in memory.

Interline offset must be word aligned.

After any changes to this register write to the COMMIT register, which take effect at the next start of field

Table 855.  IRQ_LINE_THRESHOLD
Name Bit Description
IRQ line threshold 31:0 Set the IRQ line threshold in combination with setting bit 1 of IRQ_CONTROL for the IP to raise an interrupt every time it writes line number IRQ_LINE_THRESHOLD for a field.
Table 856.  OVERWRITE_BROKEN
Name Bit Description
overwrite_broken 0 If you set the overwrite_broken bit, the IP overwrites fields received where the broken bit is set in the EOF, or where the height does not match the expected height. Also the IP does not set the BUFFER_AVAILABLE bit and other buffer information registers for that field.